Coding information in integrated circuits

ABSTRACT

A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X 0 , X 1 ). Cross-talk between two electrically coupled signal paths (X 0 , X 1 ) can be utilized to perform logical computation. A signal is propagating on two signal paths (X 0 , X 1 ) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X 0 , X 1 ) determines the logic value of the output signal (X) to be produced. If the signal on the first paths (X 0 ) propagates faster than the signal on the second path (X 1 ), an output signal (X) having a first logic value is produced. If the signal on the second path (X 1 ) propagates faster than the signal on the first path (X 0 ). an output signal (X) having a second logic value is produced.

The present invention relates to a method for coding information in anelectronic circuit and an electronic circuit for coding information,said circuit comprising at least two electrically coupled signal paths.

A well-known electrical phenomenon known as cross-talk exists amongsignal paths that are electrically coupled to each other. Cross-talkmanifests itself by inducing voltage glitches on electrically coupledsignal paths, which is seen as an undesired disturbance that has to beminimized. Cross-talk also manifests itself by modifying the speed ofthe signals travelling on these signal paths. Normally, neighboringsignal paths will affect each other to a greater extent than pathslocated some distance away from each other, since the closer they arelocated to each other, the stronger the electrical coupling will be.

For instance, consider two electrically coupled signal paths in an IC.This is normally the case when two parallel extending signal paths arelocated closely together. If a signal transition occurs on a signalpath, it will propagate along the path with a given speed, reaching theend of the path within a given delay time. If, on the other hand, asignal transition occurs on both paths and the transition on each pathis in the same direction, both transitions will propagate at a higherspeed. The transitions will therefore reach the end of the path with ashorter delay. Cross-talk is thus effectively modulating the delay ofsignals propagating along signal paths being electrically coupled toeach other. These effects are in the prior art usually seen as problemsthat have to be minimized or eliminated.

For example, GB 2,089,122 discloses a semiconductor integrated circuit(IC) and seeks to reduce interference between signal lines thereof. On asubstrate of the IC, a first, second and third signal line is formed.The first signal line transmits a first signal, and the third signalline transmits a third signal having a phase which is opposite to thatof the first signal. Thus, the cross-talk from the first signal line tothe second signal line can be cancelled by the cross-talk from the thirdsignal line to the second signal line, on which a second signal istransmitted.

It is a drawback that dedicated hardware has to be added to theintegrated circuit for the sole purpose of eliminating cross-talk,especially when taking into consideration that the ongoing increase inintegration density on ICs will lead to more pronounced occurrences ofcross-talk, and a further increase in the required additional hardware,which has negative implications for the silicon real estate of the IC.

Amongst others, it is an object of the present invention to provide animproved method and electronic circuit for coding information.

This object is achieved by the invention in a first aspect in the formof a method for coding information in an electronic circuit, saidcircuit comprising at least two electrically coupled signal pathsaccording to claim 1 and in a second aspect in the form of an electroniccircuit for coding information, said circuit comprising at least twoelectrically coupled signal paths according to claim 6. This has theadvantage that cross-talk related additional hardware is utilized togenerate useful information rather than to merely eliminate or reduce aneffect that will become more and more pronounced with increasingintegration densities on ICs. So, in accordance with the invention,cross-talk is being utilized rather than being countered.

According to the first aspect of the invention, a method for codinginformation is provided wherein the relative delay between signalspropagating on at least two electrically coupled paths is determinedwhen the signals make a transition from a first logic level to a secondlogic level. An output signal is then produced having a further logiclevel depending on the relative delay between the signals.

According to the second aspect of the invention, an electronic circuitfor coding information is provided comprising means arranged todetermine the relative delay between signals propagating on at least twoelectrically coupled paths when the signals make a transition from afirst logic level to a second logic level. The electronic circuitfurther comprises means arranged to produce an output signal having afurther logic level depending on the relative delay between the signals.

The invention is based on the idea that cross-talk between twoelectrically coupled signal paths can be utilized to perform a logicalcomputation. A signal is propagating on two signal paths in the form ofeither rising or falling transitions. The relative delay between thetransitions on the two paths determines the further logic value i.e., alogic “0” or a logic “1”, of the output signal to be produced. This ishereinafter referred to as “delay coding”. If the signal on the firstpath propagates faster than the signal on the second path, an outputsignal of a first further logic value is produced. If the signal on thesecond path propagates faster than the signal on the first path, anoutput signal of a second further logic value is produced.

By employing the concept of delay coding, it is possible to implementlogic gates performing computation by means of cross-talk, which is usedto modify the speed of transitions propagating on electrically coupledsignal paths and thus modulating delays. This is advantageous sincelogic gates comprised of transistors can be replaced by logic gatescomprised of electrically coupled signal paths. Transistors are onlyneeded when conversion is to be done between the boolean domain, wheresignal values are represented by logic levels, and the delay domainwhere signal values are represented by the difference in arrival time ofsignals.

According to an embodiment of the invention, a logical signal is dividedinto two delay coded signals propagating on respective electricallycoupled signal paths. A relative delay between the two delay codedsignals is created by means of a delay encoder, e.g. a programmabledelay circuit, a buffer or some other type of circuit having an inherentdelay. Thereby, the conversion between the boolean domain, i.e., thestandard digital binary domain, and the delay coding domain isperformed. Standard delay decoders, for example metastability filters,can be used to convert delay coded signals to binary signals.

The present invention will be described in greater detail with referencemade to the accompanying drawings, in which:

FIG. 1 shows an embodiment of delay coding according to the invention;

FIG. 2 shows another embodiment of delay coding according to theinvention, in which embodiment an AND gate is implemented;

FIG. 3 shows another embodiment of delay coding according to theinvention, in which embodiment an OR gate is implemented;

FIG. 4 shows another embodiment of delay coding according to theinvention, in which embodiment an inverting gate is implemented;

FIG. 5 shows a speed-matching gate employed in the present invention;

FIG. 6 shows a typical bus structure in which the present inventionadvantageously can be employed;

FIG. 7 shows an embodiment of delay coding according to the inventionwhen used on a bus structure; and

FIG. 8 shows another embodiment of delay coding according to theinvention when used on bus structures;

FIG. 1 shows an embodiment of delay coding according to the invention.In delay coding two signal paths X0, X1 are needed for each binaryvariable X. The signal paths X0, X1 are constituted of for examplewires, copper lines on a printed circuit board, signal lines in anintegrated circuit etc. In order for cross-talk to emerge, electricalcoupling between the signal paths X0, X1 must exist, which usually isthe case among neighboring signal paths X0, X1. A signal is propagatingon both signal paths X0, X1 in the form of either rising or fallingtransitions. The relative delay A between the transitions on the twopaths X0, X1, i.e, when the signals make a transition from a first logiclevel to a second logic level, e.g., a “0”→“1” transition or a “1”→“0”transition, determines the logic value of the output signal X to beproduced. If the signal propagating on path X0 propagates faster thanthe signal on path X1, X has the logical value “0”. If the signalpropagating on path X0 propagates slower than the signal on path X1, Xhas the logical value “1”. The delay coding scheme is the same forfalling transitions. The further logic value, i.e., a logic “1” or “0”,that is assigned to the output depending on the relative delay betweenthe signals, i.e., depending on which of the signals propagates faster,is a mere matter of choice, i.e., convention. However, hereinafter theconventional delay coding scheme shown in FIG. 1 will be used.

FIG. 2 shows another embodiment of delay coding according to theinvention, in which embodiment an AND gate 200 is implemented. Asmentioned earlier, the delay encoder 120 and the delay decoder 140 arestandard electronic components utilized to make the conversion betweenthe boolean domain I and the delay coding domain II and vice versa.Assume that variables X and Y are delay coded as described in FIG. 1.The signal propagating on signal path Φ is a reference transitionsynchronized with the fastest signal propagating on either of the signalpaths X0, X1, Y0 and Y1. Three possible scenarios can occur:

-   1. Signals X and Y are both equal to logic “1”. In this case the    transitions on X1 and Y1 are faster than the transitions on X0 and    Y0 in accordance with FIG. 1 and synchronized with the reference.-   2. Signals X and Y are both equal to logic “0”. In this case the    transitions on X0 and Y0 are faster than the transitions on X1 and    Y1 in accordance with FIG. 1 and synchronized with the reference.-   3. The logical value on signals X and Y differ. In this case either    the transitions on X0 and Y1 or the transitions on X1 and Y0 are    faster in accordance with FIG. 1 and either the transitions on X0 or    Y0 are synchronized with the reference.

In case 1, the signals propagating on X0 and Y0 do not influence theneighboring reference since they are slower than the reference while Y1is accelerated by X1. Consequently, the transition on Z1 is faster thanthe transition on Z0 and thus, in accordance with FIG. 1, Z is equal tologic “1”.

In case 2, the signals on X0, X1, Y0 and Y1 are all accelerated.However, the signals propagating on X0 and Y0 now accelerate theneighboring reference. Consequently, the transition on Z0 is faster thanthe transition on Z1 and thus, in accordance with FIG. 1, Z is equal tologic “0”.

In case 3, either the signals propagating on X0 or Y0 are synchronizedwith the neighboring reference and, as a consequence, are able toaccelerate the reference. As the signal on Y1 is not accelerated, thetransition on Z0 is faster than the one on Z1. Consequently, inaccordance with FIG. 1, Z is equal to logic “0”.

Hence, studying these three cases, it can be seen that the circuit inFIG. 2 implements an AND gate 200.

By applying a similar reasoning, the function of an OR gate 300 as shownin FIG. 3 can be verified.

It will be understood by those skilled in the art that in the context ofthe present invention, the verb ‘to accelerate’ is used to indicate thedifference between a signal propagation speed on a wire caused byadvantageous signal propagations on neighboring wires, and a signalpropagation speed on a wire having no advantageous signal propagationson its neighboring wires, leaving the signal propagation on the wire tobe more hampered by cross-talk with its environment. Consequently, thesignal propagation speed in the first situation is better than thesignal propagation speed in the second situation, hence the signalpropagation on the wire in the first situation is ‘accelerated’ withrespect to the signal propagation of the wire in the second situation.It is stipulated that the use of the verb ‘to accelerate’ as used in theaforementioned context should not necessarily be explained as anindication of an increase of the actual speed of a signal propagation onthe wire.

FIG. 4 shows another embodiment of a delay coding circuit according tothe invention, in which embodiment an inverter 400 is implemented. WhenX is equal to logic “0”, the transition on X0 is faster than thetransition on X1, resulting in a logic “1” on Z, in accordance with theconventional delay coding as explained in FIG. 1 and its detaileddescription. When X is equal to logic “1”, the transition on X1 isfaster than the transition on X0, resulting in a logic “0” on Z, inaccordance with the delay coding as shown in FIG. 1.

FIG. 5 shows a speed-matching gate 500 employed in the presentinvention. An important factor in interference delay logic is thatsignals such as the reference have the proper speed, i.e., awell-defined speed. A signal propagating over a wire in a randomenvironment will always exhibit some delay resulting from theinteraction of the wire with the environment. In contrast, a wire froman interacting wire pair employing the techniques of the presentinvention may have a smaller delay than the delay from a randomenvironment, because the cross-talk with the neighboring wire in thewire pair may be reduced due to the fact that both wires may carrymatching transient signals. Consequently, in an arrangement where asubstantial number of gates according to the invention are cascaded,signals propagating through these gates may substantially benefit fromthis effect, and properly accelerated references, i.e., references thatexhibit optimized signal propagation speeds resulting from advantageoussignal propagations on interacting wires, which match this beneficialeffect must be provided to ensure that the reference still defines theupper limit of the signal propagation speed. Speed-matching gates arethus required. An example of such a gate is illustrated in FIG. 5. Thespeed-matching gate 500 has two output terminals, i.e., output terminals520 and 530. The propagation speed of the signal on the wire X1 isimproved by adding an interacting open output terminal 530 to outputterminal 520, the latter being coupled to a receiver 504. Drivers 502are included in both output terminals 520 and 530 to reduce the load onthe wire X1, in order to allow for an optimization of the propagationspeed of the signal. Because the switching behavior on output terminal530 matches the switching behavior on output terminal 520, thecross-talk between the output terminal 520 and its environment isreduced, thus reducing the effects of cross-talk on the output terminal520, which improves the propagation speed of the signal on outputterminal 520. Drivers 502 and receiver 504 may be implemented by anybuffer or driver known from the art.

As previously mentioned, transistors are only needed in the form ofdelay encoders 120 and delay decoders 140 when conversion is to be donebetween the boolean domain I, where signal values are represented bylogic levels, and the delay coding domain II where signal values arerepresented by the difference in arrival time of signals. The relativenumber of transistors used in a logical network decreases as the numberof cascaded gates increases, since all logical computations can beperformed in the delay coding domain II and transistors are necessaryonly at the interfaces between the two domains I and II. An extensivenetwork of delay coded gates would still only need transistors at theinterfaces. Possibly, simple transistor buffers, e.g. drivers 502, areused to amplify the signals propagating on the signal paths, i.e.,output terminals 520 and 530. The two wires each have an own driver 502in order for acceleration to take place. Note that the length of the twowires is a design parameter; the longer the parallel run length of thetwo wires, the more acceleration is obtained.

Delay coding according to the invention can preferably be used ininterconnections for electrical signals. Interconnections, e.g., busseson a printed circuit board, are passive components for transmissions ofbits from one place to another. FIG. 6 shows a typical bus structure 600containing flip-flops 1, buffers 2 and wires 3 for amplification ofsignals propagating on the wires. By using delay coding, logicalcomputations can be performed on the busses while transmitting thesignals.

FIG. 7 shows a circuit 700 implementing an embodiment of delay codingaccording to the invention when used on a bus structure or anothermultiple-wire arrangement. A data wire 610 is split into a program wire620 and a signal wire 630. As described earlier, computation can only beperformed when a transition takes place on the data wire 610. The signalwire 630 and the program wire 620 must be electrically coupled to eachother in order to employ the effects of cross-talk, i.e., modifying thespeed of the signal propagating on the signal wire 630. Synchronizationof the program wire 620 and the signal wire 630 is an important issue,since the delay modification caused by the program wire 620 on thesignal wire 630 should preferably be maximised. As described earlier, astandard delay decoder 140 can be used to convert delay coded signals tobinary signals by comparing the transient behavior on signal wire 630with that of reference wire 640. The wires 610, 620, 630, 640 may beequipped with appropriate driver circuits 602 to obtain the desiredsignal strength on the wires.

The principle of the logic computation will be described in thefollowing. By default, the signal propagating on the reference wire 640(which can be shared with other signal wires) is faster than the signalpropagating on the signal wire 630. This produces a logic value of “0”on the Z_EXTRA output of delay decoder 140. However, if the computationconditions are met, i.e. a*(b+c), the signal propagating on the signalwire will be accelerated by the signal propagating on the program wire620. Hence, Z_EXTRA will be equal to logic “1” and the logical functionZ_EXTRA=a*(b+c) has been implemented. By swapping the inputs X and Y ofthe delay decoder 140, the inverse function is implemented. It should beclear that this particular logic function merely is exemplifying, andany logic function can be implemented. As can be seen in FIG. 7, thedelay encoder 120 is, as mentioned previously, implemented by means oftransistors 122 and 124.

FIG. 8 shows another embodiment of delay coding according to theinvention when used on bus structures or other multiple-wirearrangements. Here, the circuit 700 in FIG. 7 is represented by a blockfollowed by a repeater 720. The block 700 and the repeater 720 forms astage. Each stage can perform computing and employ data from theprevious stages. The conventional transmission path for busses includesthe signals propagating via “Data” and “Z”. Variables a, b, and crepresent additional data transportation and Z_EXTRA representsadditional computed data transportation. Note that data transport maytake place without the performance of computation.

When cascading the stages as in FIG. 8, conversion is made from theboolean domain I to the delay coding domain II for each stage. Whenpassing the data on to next stage, conversion is made from the delaycoding domain II to the boolean domain I.

It should be noted that the above-mentioned embodiments illustraterather than limit the invention, and that those skilled in the art willbe able to design many alternative embodiments without departing fromthe scope of the appended claims. In the claims, any reference signsplaced between parentheses shall not be construed as limiting the claim.The word “comprising” does not exclude the presence of elements or stepsother than those listed in a claim. The word “a” or “an” preceding anelement does not exclude the presence of a plurality of such elements.In the device claim enumerating several means, several of these meanscan be embodied by one and the same item of hardware. The mere fact thatcertain measures are recited in mutually different dependent claims doesnot indicate that a combination of these measures cannot be used toadvantage.

1. A method for coding information in an electronic circuit, saidcircuit comprising at least two electrically coupled signal pathscharacterized in that the method comprises the steps of: determining aninformation bit to be encoded; encoding the information bit as afunction of the relative delay between signals propagating on said pathswhen said signals make a transition from a first logic level to a secondlogic level; and producing as an output signal said information bitaccording to the relative delay between said signals.
 2. The methodaccording to claim 1, further comprising the step of: dividing a logicalsignal into two signals to be propagated on a respective one of saidsignal paths.
 3. The method according to claim 1, further comprising thestep of: creating a reference signal being synchronized with the fastestsignal propagating on either of said signal paths.
 4. The methodaccording to claim 1, further comprising the step of: creating arelative delay between the signals propagating on said signal paths. 5.The method according to claim 1, wherein the producing step is performedby means of a delay decoder.
 6. An electronic circuit for codinginformation, said circuit comprising at least two electrically coupledsignal paths characterized in that the circuit comprises: means fordetermining an information bit to be encoded; means for encoding theinformation bit as a function of the relative delay between signalspropagating on said paths when said signals make a transition from afirst logic level to a second logic level; and means for producing as anoutput signal said information bit depending on the relative delaybetween said two signals.
 7. The circuit according to claim 6, furthercomprising: means for dividing a logical signal into two signals to bepropagated on a respective one of said signal paths.
 8. The circuitaccording to claim 6, further comprising: means for creating a referencesignal (D) being synchronized with the fastest signal propagating oneither of said signal paths.
 9. The circuit according to claim 6,further comprising: means for creating a relative delay between thesignals propagating on said signal paths.
 10. The circuit according toclaim 6, wherein the producing means comprise a delay decoder.